(1) Field of the Invention
This invention relates generally to digital-to-analog converters (DAC) and relates more specifically to three-level DACs applying dynamic element matching (DEM) techniques.
(2) Description of the Prior Art
A digital-to analog converter (DAC) is a device for converting a digital (usually binary) code to an analog signal (current, voltage or electric charge). The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers) into a continuously varying physical quantity, usually an analogue electrical voltage.
In an ideal DAC, the numbers are output as a sequence of impulses, that are then filtered by a reconstruction filter. The DAC fundamentally converts finite-precision numbers (usually fixed-point binary numbers) into a continuously varying physical quantity, usually an analogue electrical voltage.
In an ideal DAC, the numbers are output as a sequence of impulses, that are then filtered by a reconstruction filter. This would, in principle, reproduce a sampled signal precisely up to the Nyquist frequency, although a perfect reconstruction filter cannot be practically constructed as it has infinite phase delay; and there are errors due to quantization.
Instead of impulses, usually the sequence of numbers update the analogue voltage at uniform sampling intervals.
These numbers are written to the DAC, typically with a clock signal that causes each number to be latched in sequence, at which time the DAC output voltage changes rapidly from the previous value to the value represented by the currently latched number. The effect of this is that the output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant or ‘staircase’ shaped output. This is equivalent to a zero-order hold operation and has an effect on the frequency response of the reconstructed signal.
The fact that practical DACs output a sequence of piecewise constant values or rectangular pulses would cause multiple signal images above the Nyquist frequency. The signal images result from the sampling process, i.e. they are already in the digital input of the DAC. These signal images are typically removed with a low pass filter acting as a reconstruction filter.
However, this filter means that there is an inherent effect of the zero-order hold on the effective frequency response of the DAC resulting in a mild roll-off of gain at the higher frequencies (often a 3.9224 dB loss at the Nyquist frequency) and depending on the filter, phase distortion. This high-frequency roll-off is the output characteristic of the DAC, and is not an inherent property of the sampled data.
Multi-bit delta-sigma DACs offer many advantages over single-bit delta-sigma DACs, such as much increased stable input range, less likelihood of unacceptable modulator tones and improved tolerance to clock jitter in the digital-to-analog conversion step. However, mismatches (such as random manufacturing variations) between the unit elements used to build a multi-bit DAC can cause non-linearity in the DAC transfer function, which causes signal distortion when converting a distortion-free digital signal to an analog signal. To achieve low distortion and a high signal-to-noise ratio (SNR), multi-bit DACs typically use dynamic element matching (DEM) techniques; these cause the element mismatches to generate an out-of-band noise-shaped noise instead of in-band distortion components. The resulting out-of-band noise energies can be removed by post-filtering if required. Various DEM methods are known for multi-bit DACs made of unit elements with two states (e.g. switched capacitor DACs using two reference voltages or switched current DACs using two reference currents). If 3-state unit elements can be used then it may be possible to reduce the number of DAC elements required (i.e. circuit complexity) to achieve a certain number of binary bits equivalent analog outputs levels.
A further known issue with most switched capacitor DACs implementations is signal-dependent loading of the DAC reference voltages, which can lead to signal distortion. One way to remove signal dependency is to always draw the maximum reference current, but this maximizes reference power, which is undesirable in low-power systems. Techniques which reduce the current from the reference can reduce distortion and power. It is a challenge for the designers of DACs to reduce therefore the peak reference current significantly compared to prior art.
There are known patents, patent publications or other publications dealing with the design of DACs:
U.S. Patent Publication (US 2005/0156773) to Galton proposes an improvement to a conventional multistage pipelined Analog-to-Digital Converter (ADC) having multiple stages, connected one to the next by an interstage amplifier, each stage with a flash digital-to-analog converter (DAC), a digital-to-analog converter (DAC) producing an associated intermediate analog signal, a subtractor of intermediate analog signals to produce an analog difference signal fed to the interstage amplifier of a next following stage, and a thermometer encoder producing an associated digital output signal; the improvement directed to canceling noise resultant from component mismatch, particularly mismatched capacitors paired with a first-stage DAC of the ADC. The improved ADC uses in at least a first, and preferably two, stages a flash DAC of a dynamic element matching (DEM) type producing, as well as an associated intermediate analog signal, random bits and parity bits; a Digital Noise Cancellation (DNC) logic circuit, receiving the random bits and the parity bits and a digitized residue sum of the digital output signal's arising from all stages beyond a stage of which the DNC logic circuit is a part, so as to produce an error estimate for the stage; and a subtractor subtracting the error estimates of the DNC logic circuits from the combined digital output signal of all higher stages in order to produce a corrected ADC digital output signal. A 14-bit 4-stage pipelined ADC having, by way of example, a theoretical optimum conversion precision of 14.1 bits and a realistic conversion precision of 10.4 bits, is enhanced by modestly-sized and continuously-automatically-operative DNC to realize 13.3 bits conversion precision.
U.S. Patent Publication (US 2008/0309536 to Le Guillou) discloses an analog-to-digital converter of the Sigma Delta type provides a stream of digital output samples (OUT) in response to an analog input signal. The analog-to-digital converter comprises a quantizer that has a dead zone. The quantizer provides a digital output sample that has a mid-point value when the quantizer receives an input signal whose amplitude is within the dead zone. A feedback path within the analog-to-digital converter provides a feedback action only in response to a digital output sample that has a value other than the mid-point value.
(U.S. Pat. No. 7,079,063 to Nguyen et al.) teaches a system for processing digital signals in a data converter. The system includes a thermometer encoder for receiving signed binary data and for providing signed thermometer data. The signed thermometer data includes positive thermometer data and negative thermometer data. The system also includes a shuffler that receives positive input data responsive to the positive thermometer data and receives negative input data responsive to the negative thermometer data. The system also includes a decoder for receiving output data from the shuffler and providing decoded data to an analog output stage. It is a tri-level DEM method by analog devices using a shuffler-based design.
Furthermore K. Nguyen has published: “A 101 dB SNR, 1.1 mW Oversampling Audio DAC with A Three-level DEM Technique”, K. Nguyen, A. Bandyopadhyay, B. Adams, K. Sweetland, P. Baginski, Journal of Solid-State Circuits, December 2008, vol. 43 no. 12, pp 2592-2600 and
ISSC 2008, pp 488-489 “A 108 db SNR 1.1 mW Oversampling Audio DAC with a three level DEM Technique” by K. Nguyen, A, Bandyopadhyay, R. Adams, K. Sweetland and P. Baginski) is based on the patent (U.S. Pat. No. 7,079,063 to Nguyen et al.) cited above explaining some advantages of a tri-level DAC implementation.
(U.S. Pat. No. 6,952,176 to Frith et al.) discloses generally digital-to-analogue converters and relates more particularly to techniques for reducing signal dependent loading of reference voltage sources used by these converters. A differential switched capacitor digital-to-analogue (DAC) circuit comprises first and second differential signal circuit portions for providing respective positive and negative signal outputs with respect to a reference level, and has first and second reference voltage inputs for receiving respective positive and negative references. Each of said first and second circuit portions comprises an amplifier with a feedback capacitor, a second capacitor, and a switch to switchably couple said second capacitor to a selected one of said reference voltage inputs to charge the second capacitor and to said feedback capacitor to share charge with the feedback capacitor. The switch of said first circuit portion is further configured to connect said second capacitor of said first circuit portion to share charge with said feedback capacitor of said second circuit portion; and the switch of said second circuit portion is further configured to connect said second capacitor of said second circuit portion to share charge with said feedback capacitor of said first circuit portion. This enables the second capacitors to in effect be alternately pre-charged to positive and negative signal-dependent nodes so that, on average, signal dependent loading of the references is approximately constant.
This patent teaches signal dependent loading in switched capacitor DAC implementations, it results in constant reference loading, hence causes no signal dependent loading, but it is not low reference power because it is constantly maximum loading.
(U.S. Pat. No. 6,573,850 to Pennock) describes a switched capacitor digital-to-analogue converter (DAC) 400 for reducing signal dependent loading of a reference voltage source used by the converter comprises an active circuit with a feedback element. The feedback element comprises a feedback capacitor, a second capacitor (106) and switches to connect the second capacitor to one of first and second reference sources to store charge on the second capacitor and to connect the second capacitor in parallel with the feedback capacitor to share said stored charge with the feedback capacitor. The switch is further configured to connect the second capacitor to a substantially signal-independent reference prior to connection of the second capacitor to said one of said first and second references. Connecting the second capacitor to a substantially signal-independent reference source prior to the selected first or second reference gives a linear signal-dependent loading of the first and second reference sources. Connecting two such circuits with anti-phase signals then causes these linear dependences to cancel, giving a substantially signal-independent loading of these reference sources.
This patent is a precursor patent to (U.S. Pat. No. 6,952,176 to Frith et al.) cited above and is also related to signal dependent loading in switched-capacitor DAC implementations. Adding a discharge phase in the clocking arrangement removes all traces of signal from the DAC capacitors before they are switched to the reference, This achieves signal independence but makes the clock generation more complicated and results in maximum reference loading for all digital input codes. (i.e. higher power dissipation).
(U.S. Pat. No. 5,274,375 to Thompson) describes an analog-to-digital converter including a two-bit delta-sigma modulator. The delta-sigma modulator is comprised of a first stage integrator that feeds a noise shaping circuit. The output of the noise shaping circuit is input to a two-threshold imbedded ADC to provide the two-bit output. This output of the imbedded ADC is input to a digital filter to provide the filtered digital output, this filtering high-frequency noise. The output of the imbedded ADC is also fed back through a three-level DAC to a summing junction on the input of the integrator. The three-level DAC has three states that are output with one state being a “do nothing” state. The thermal noise performance of the delta-sigma modulator as a function of the quantizer threshold voltages is first simulated and then the value of the quantizer thresholds selected to provide optimum signal-to-thermal noise performance.
Furthermore Thompson has published: “A Digitally-Corrected 20b Delta-Sigma Modulator”, C. D. Thompson, S. R. Bernadas, ISSCC, 1994, pp 194-195.
IEEE Press/John Wiley &Sons Inc., 2005, ISBN 0-471-46585-2 “Understanding Delta Sigma Data Converters” by R. Schrier and G. C. Temes, particularly chapter 6 sections 6.3 and 6.4 for general overview of DEM and mismatch shaping and key references.
IEEE Press, 1997, ISBN 0-7803-1045-4 “Delta Sigma Data Converters: Theory, Design and Simulation” by S. R. Norsworthy, R. Schrier and G. C. Temes, particularly chapter 8 section 3 for multi-bit converter linearity techniques, general overview and key references.
IEEE Trans. Circuits and Systems-II, Vol. 42, No. 12, December 1995, pp 753-762 “Linearity Enhancement of Multi-bit ΔΣ A/D and D/A Converters Using Data Weighted Averaging” by R. T. Baird and T. S. Fiez, introducing Data weighed Averaging (DWA) rotational DEM method.
IEEE Trans. Circuits and Systems-II, Vol. 47, No. 11, November 2000, pp 1137-1144, “Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in Δ-Σ Modulators” by M. Vadipour, discusses ways to suppress tones that can be generated by the DWA algorithm.
FIG. 1 prior art shows a typical implementation for a level N+1 level multi-bit DAC using the well known direct charge transfer (DCT) method. The implementation shown is single-ended though differential implementations and their relative advantages are obvious and well-known to practitioners. This DAC generates a multi-level output by combining N elements with two output levels (here V+ and V−) as controlled by the binary digit inputs D1-DN.
D1-DN are single bit binary inputs which may be derived by, for example, but not limited to, decoding a binary weighted digital input to the DAC (e.g. a M bit binary input could be expanded to a N=2M bit population code such as thermometer code). CK1 and CK2 are simplified-for-illustration non-overlapping clocks used to transfer charge from the reference voltages V+ and V− to the output capacitor COUT; various S/C circuit clocking schemes and their advantages are well-known to practitioners. Capacitors C1 to CN have equal capacitances. This DAC has N+1 analog levels.
In case the DAC is clocked repeatedly with m (m can take values 0, 1, . . . , N) of the DN inputs set to 1 and the remaining bits set to 0 then the steady state output voltage of the DAC is:
  Vout  =                    (                  V          -                )            +                        m          N                ×                  (                      V            +                          -              V                        -                    )                      =                            n          M                ×                  (                      V            +                    )                    +                                    1            -            m                    N                ×                  (                      V            -                    )                    
As m of the input capacitors C1-CN are being switched repeatedly between Vout and V+, the charge drawn from the V+ reference voltage on each cycle is thus:
            Q      +=              m        ×        C        ×        Δ        ⁢                                  ⁢        V              =                  m        ×        C        ×                  (                      V            +                          -              Vout                                )                    =                        (                      V            +                          -              V                        -                    )                ×        m        ×        C        ×                  (                      1            -                          m              N                                )                      ,where C is the nominal value of each of the C1-CN capacitor units. It can be shown that the charge Q− injected into the negative reference voltage V− has the same magnitude as Q+ (as would be hoped under steady-state otherwise the DAC is accumulating charge!). the reference charge is a quadratic function of the DAC input code, m. It is zero for m=0 and M=N and reaches a maximum for m=N/2 if N is even, otherwise it is maximum for m=N/2+/−0.5. The example of FIG. 2 prior art shows reference charge Q+ versus DAC input code for the case N=32.
Similar quadratic expressions can be derived for the reference charges Q+ and Q− in differential DAC implementations.
A well known problem with dependency of the reference charge on the DAC input code is that providing this charge requires a current to flow from or to the reference voltage source, and this current flow can modify the reference voltage through interaction with the reference sources output impedances (e.g. ohmic drop). Any signal-dependent variation of the reference voltages with changing DAC input causes non-linearity of the DAC analog output versus digital input code transfer function, and subsequent distortion of any signals being converted to analog. It is thus desirable to reduce reference current variation to reduce distortion (see prior art patents referenced).
A further well-known serious problem with multi-bit S/C (and current steering) DACs is that the individual DAC unit elements, C1-CN, cannot be manufactured to be exactly equal, but will have unavoidable random variations from ideal (“mismatches”) due to manufacturing variations. These mismatches can cause nonlinearity of the DAC transfer function and hence distortion of any digital signals being converted to analog. Various techniques are known to reduce the distorting effect of these mismatches, such as trimming, digital correction and DEM. DEM methods use scrambling techniques to vary the order in which the DAC elements are used every time a digital input code is presented, such that the energy in the DAC output spectrum caused by the mismatches appears as out-of-band noise instead of causing in-band distortion or noise. Various DEM methods for DACs constructed with 2-level unit elements (e.g. switched capacitor DACs with only two reference voltages V+ and V−) are well known to practitioners (as described by prior art references above).
The Data Weighted Averaging (DWA) method scrambles the DAC elements by selecting adjacent elements rotated circularly by the number of elements used as outlined in IEEE Trans. Circuits and Systems-II, Vol. 42, No. 12, December 1995, pp 753-762 “Linearity Enhancement of Multi-bit ΔΣ A/D and D/A Converters Using Data Weighted Averaging” by R. T. Baird and T. S. Fiez. This converts the effects of mismatches to a first-order shaped noise in the DAC output spectrum. FIG. 3 prior art shows an example of the DWA algorithm applied to a multi-bit DAC constructed using 8 elements with 2-levels per element (+1 and −1 indicate the DAC element state, e.g. a capacitor element switched to V+ or V− in S/C DAC implementations).
As outlined above, techniques which reduce the current from the reference can reduce distortion and power. It is a challenge for the designers of DACs to reduce therefore the peak reference current significantly compared to prior art.